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<title>INSERTPS—Insert Scalar Single-Precision Floating-Point Value </title></head>
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<h1>INSERTPS—Insert Scalar Single-Precision Floating-Point Value</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>66 0F 3A 21 /r ib INSERTPS xmm1, xmm2/m32, imm8</td>
<td>RMI</td>
<td>V/V</td>
<td>SSE4_1</td>
<td>Insert a single-precision floating-point value selected by imm8 from xmm2/m32 into xmm1 at the specified destination element specified by imm8 and zero out destination elements in xmm1 as indicated in imm8.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F3A.WIG 21 /r ib</p>
<p>VINSERTPS xmm1, xmm2, xmm3/m32, imm8</p></td>
<td>RVMI</td>
<td>V/V</td>
<td>AVX</td>
<td>Insert a single-precision floating-point value selected by imm8 from xmm3/m32 and merge with values in xmm2 at the specified destination element specified by imm8 and write out the result and zero out destination elements in xmm1 as indicated in imm8.</td></tr>
<tr>
<td>EVEX.NDS.128.66.0F3A.W0 21 /r ib VINSERTPS xmm1, xmm2, xmm3/m32, imm8</td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Insert a single-precision floating-point value selected by imm8 from xmm3/m32 and merge with values in xmm2 at the specified destination element specified by imm8 and write out the result and zero out destination elements in xmm1 as indicated in imm8.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RMI</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>Imm8</td>
<td>NA</td></tr>
<tr>
<td>RVMI</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>Imm8</td></tr>
<tr>
<td>T1S</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv</td>
<td>ModRM:r/m (r)</td>
<td>Imm8</td></tr></table>
<h2>Description</h2>
<p>(register source form)</p>
<p>Select a single-precision floating-point element from second source as indicated by Count_S bits of the immediate operand and destination operand it into the first source at the location indicated by the Count_D bits of the imme-diate operand. Store in the destination and zero out destination elements based on the ZMask bits of the imme-diate operand.</p>
<p>(memory source form)</p>
<p>Load a floating-point element from a 32-bit memory location and destination operand it into the first source at the location indicated by the Count_D bits of the immediate operand. Store in the destination and zero out destination elements based on the ZMask bits of the immediate operand.</p>
<p>128-bit Legacy SSE version: The first source register is an XMM register. The second source operand is either an XMM register or a 32-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.</p>
<p>VEX.128 and EVEX encoded version: The destination and first source register is an XMM register. The second source operand is either an XMM register or a 32-bit memory location. The upper bits (MAX_VL-1:128) of the corresponding register destination are zeroed.</p>
<p>If VINSERTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an #UD exception.</p>
<h2>Operation</h2>
<p><strong>VINSERTPS (VEX.128 and EVEX encoded version)</strong></p>
<pre>IF (SRC = REG) THEN COUNT_S (cid:197) imm8[7:6]
    ELSE COUNT_S (cid:197) 0
COUNT_D (cid:197) imm8[5:4]
ZMASK (cid:197) imm8[3:0]
CASE (COUNT_S) OF
    0: TMP (cid:197) SRC2[31:0]
    1: TMP (cid:197) SRC2[63:32]
    2: TMP (cid:197) SRC2[95:64]
    3: TMP (cid:197) SRC2[127:96]
ESAC;
CASE (COUNT_D) OF
    0: TMP2[31:0] (cid:197) TMP
         TMP2[127:32] (cid:197) SRC1[127:32]
    1: TMP2[63:32] (cid:197) TMP
         TMP2[31:0] (cid:197) SRC1[31:0]
         TMP2[127:64] (cid:197) SRC1[127:64]
    2: TMP2[95:64] (cid:197) TMP
         TMP2[63:0] (cid:197) SRC1[63:0]
         TMP2[127:96] (cid:197) SRC1[127:96]
    3: TMP2[127:96] (cid:197) TMP
         TMP2[95:0] (cid:197) SRC1[95:0]
ESAC;
IF (ZMASK[0] = 1) THEN DEST[31:0] (cid:197) 00000000H
    ELSE DEST[31:0] (cid:197) TMP2[31:0]
IF (ZMASK[1] = 1) THEN DEST[63:32] (cid:197) 00000000H
    ELSE DEST[63:32] (cid:197) TMP2[63:32]
IF (ZMASK[2] = 1) THEN DEST[95:64] (cid:197) 00000000H
    ELSE DEST[95:64] (cid:197) TMP2[95:64]
IF (ZMASK[3] = 1) THEN DEST[127:96] (cid:197) 00000000H
    ELSE DEST[127:96] (cid:197) TMP2[127:96]
DEST[MAX_VL-1:128] (cid:197) 0</pre>
<p><strong>INSERTPS (128-bit Legacy SSE version)</strong></p>
<pre>IF (SRC = REG) THEN COUNT_S (cid:197)imm8[7:6]
    ELSE COUNT_S (cid:197)0
COUNT_D (cid:197)imm8[5:4]
ZMASK (cid:197)imm8[3:0]
CASE (COUNT_S) OF
    0: TMP (cid:197)SRC[31:0]
    1: TMP (cid:197)SRC[63:32]
    2: TMP (cid:197)SRC[95:64]
    3: TMP (cid:197)SRC[127:96]
ESAC;
CASE (COUNT_D) OF
    0: TMP2[31:0] (cid:197)TMP
         TMP2[127:32] (cid:197)DEST[127:32]
    1: TMP2[63:32] (cid:197)TMP
         TMP2[31:0] (cid:197)DEST[31:0]
         TMP2[127:64] (cid:197)DEST[127:64]
    2: TMP2[95:64] (cid:197)TMP
         TMP2[63:0] (cid:197)DEST[63:0]
         TMP2[127:96] (cid:197)DEST[127:96]
    3: TMP2[127:96] (cid:197)TMP
         TMP2[95:0] (cid:197)DEST[95:0]
ESAC;
IF (ZMASK[0] = 1) THEN DEST[31:0] (cid:197)00000000H
    ELSE DEST[31:0] (cid:197)TMP2[31:0]
IF (ZMASK[1] = 1) THEN DEST[63:32] (cid:197)00000000H
    ELSE DEST[63:32] (cid:197)TMP2[63:32]
IF (ZMASK[2] = 1) THEN DEST[95:64] (cid:197)00000000H
    ELSE DEST[95:64] (cid:197)TMP2[95:64]
IF (ZMASK[3] = 1) THEN DEST[127:96] (cid:197)00000000H
    ELSE DEST[127:96] (cid:197)TMP2[127:96]
DEST[MAX_VL-1:128] (Unmodified)</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VINSERTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int nidx);</p>
<p>INSETRTPS __m128 _mm_insert_ps(__m128 dst, __m128 src, const int nidx);</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None</p>
<h2>Other Exceptions</h2>
<p>Non-EVEX-encoded instruction, see Exceptions Type 5; additionally</p>
<table class="exception-table">
<tr>
<td>
<p>#UD</p>
<p>EVEX-encoded instruction, see Exceptions Type E9NF.</p></td>
<td>If VEX.L = 0.</td></tr></table></body></html>